In advanced field effect transistor (FET) designs, to improve FET performance it has been proposed to decrease the thickness of the gate electrode depletion layer formed when the FET is turned on. That is, as the physical dimensions of the FET decrease and electric field intensity in the channel region increase, the thickness of the depletion layer formed within the polysilicon gate electrode increases. This thickened depletion layer reduces the effectiveness of the gate electrode potential in controlling channel conduction, and thus degrades device performance. Conventional doping processes have been employed to dope the polysilicon electrode simultaneously with the FET source/drains. With this method, however, electrode carrier depletion effects are overly influenced by the required doping concentration of the source/drains near the gate dielectric of the FET being fabricated, and the required source/drain doping levels are not the best levels for achieving thin depletion layers in the electrode. Another method has been to pre-dope the polysilicon layer before etching the polysilicon layer into gate electrodes, thus decoupling the gate doping process from the source/drain doping process. However, it has been found that the resultant gate electrodes have severe image size control and reliability problems due to the presence of electrode material having widely differing dopant concentrations. Therefore, there is a need for a method of fabricating an FET with reduced gate electrode depletion layer thickness when the device is turned on.